DAC5674IPHPG4【PDF 11/39 页】IC DAC 14BIT 400MSPS 48-HTQFP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录1992

7页 8页 9页 10页 [11页]12页 13页 14页 15页

DAC5674

SLWS148A SEPTEMBER 2003 REVISED OCTOBER 2005

www.ti.com

080

IF=32

160

240

320

112

208

100

IF=40

200

300

400

260

140

065

IF=26

130

195

260

169

”Sinx/x”

Attenuation

Fupdate+65 MSPS

*1.83 dB

*7.2 dB

”Sinx/x”

Attenuation

Fupdate+80 MSPS

*1.83 dB

*7.2 dB

”Sinx/x”

Attenuation

Fupdate+100 MSPS

*1.83 dB

*7.2 dB

Figure 20. High-Pass 4

y Interpolation Filter Operation: Example Frequencies

Clock Generation Function

An internal phase-locked loop (PLL) or external clock can be used to derive the internal clocks (1

×, 2×, and 4×)

for the logic, FIR interpolation filters, and DAC. Basic functionality is depicted in Figure 21. Power for the internal

PLL blocks (PLLVDD and PLLGND) is separate from the other clock generation blocks power (CLKVDD and

CLKGND), thus minimizing phase noise within the PLL. The PLLVDD pin establishes internal/external clock

mode: when PLLVDD is grounded, external clock mode is active and when PLLVDD is 3.3 V, internal clock mode

is active.

In external clock mode, the user provides a differential external clock on pins CLK/CLKC. This clock becomes

the 4

× clock and is twice divided down to generate the 2× and 1× clocks. The 2× or 1× clock is multiplexed out

on the PLLLOCK pin to allow for external clock synchronization.

In internal clock mode, the user provides a differential external reference clock on CLK/CLKC. A type four

phase-frequency detector (PFD) in the internal PLL compares this reference clock to a feedback clock and

drives the PLL to maintain synchronization between the two clocks. The feedback clock is generated by dividing

the VCO output by 1

×, 2×, 4×, or 8×, as selected by the prescaler (DIV[1:0]). The output of the prescaler is the

× clock, and is divided down twice to generate the 2× and 1× clocks. Pin X4 selects the 1× or 2× clock to clock

in the input data; the selected clock is also fed back to the PFD for synchronization. The PLLLOCK pin is an

output indicating when the PLL has achieved lock. An external RC low-pass PLL filter is provided by the user

at pin LPF. See the Low-Pass Filter section for filter setting calculations. Table 4 provides a summary of the

clock configurations with corresponding data rate ranges.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式